Mem-Apr 5, 2007
From STDFGroup
STDF Memory Datalog meeting Notes
Date*: 5th Apr 2007
Attendees:
Kochen Liao -- Qualcomm
Liang Lai -- Mentor Graphics
John Rowe -- Teradyne
Sauro Landini -- ARM
Ajay Khoche -- Verigy
Ping Wen -- Yield Dynamics
Sergey Shekyan -- Virage Logic
Agenda:
- Review of Virage Logic Memory Bitmap requirements
Minutes:
- The group reviewed the the requirement document from Virage Logic
- Following observations were made
- datalog can be in either ASCII or Binary format defined/used by the customer. Virage creates customer parsers for the supported format and currently has parsers for Credence and Advantest tester logs/formats
- datalog is in raw format i.e. failed vector format. which is compared with simulation log to get the row/col information in the datalo processing tool. that generates error count and detailed fail information in .bitfail file
- Bitfail file is used by the Virage Logic's visualization tools or 3rd part visulaization tools
- All the fields in the bitfail file are generated for each dice for which datalog is collected
- Datalog is done only during the ramp and not in the production
- very small no of dice are used for data collection
- loading 1 wafer full of datalog takes about 12hrs to load and then 30mins to process
- Yield Dynamics does not load the entire data to does not incur the load time. The processing times for them are about .5-1Hr
Action Items:
- Get PDF to present their requirements (Ajay)
- get Cadence representative in the group (Sergey)
- Prepare starting requirements document (Ajay)
- Review ST' proposal (All)
